The present invention relates to a semiconductor memory device and more particularly to an electrically erasable programmable read only memory (hereinafter referred to as EEPROM).
An EEPROM having a NAND type cell structure is proposed as a conventional one. The EEPROM includes a plurality of memory cells each having an n-channel MOSFET in which a control gate and a floating gate are stacked one on another as a charge storage electrode. The memory cells are connected in series such that their adjacent ones share a source and drain. These memory cells as one unit are connected to a bit line. A plan view of one NAND cell is shown in FIG. 1A and its equivalent circuit is shown in FIG. 1B.
FIGS. 2A and 2B are cross-sectional views taken along lines IIA--IIA and IIB--IIB of FIG. 1A, respectively. A memory cell array constituted of a plurality of NAND cells is formed on a p-type silicon substrate (or p-well) 5 surrounded with a device isolation oxide film 6. The NAND cell of FIG. 1A is constituted of eight memory cells M.sub.1 to M.sub.8 connected in series shown in FIG. 1B.
As illustrated in FIG. 2B, each of the memory cells has a floating gate 14 formed on the substrate 5 with a gate insulator film 7 therebetween. As is apparent from FIGS. 1A and 2A, the floating gate 14 is one of a plurality of floating gates 14.sub.1, 14.sub.2, . . . , 14.sub.8. The memory cells are connected in series such that adjacent ones share an n.sup.+ diffusion layer 8 serving as both a source and a drain.
As illustrated in FIGS. 1A and 2A, first select gates 14.sub.9 and 16.sub.9 and second select gates 14.sub.10 and 16.sub.10 are formed on the drain and source sides of the NAND cell at the same time when the floating gate and control gate of each memory cell are done. The substrate 5 on which the NAND cell is formed, is covered with a CVD oxide film 10 and a bit line 11 is arranged thereon. In FIGS. 2A and 2B, reference numeral 9 indicates an oxide film for isolating the floating gate 14 and control gate 16 from each other.
The control gates 16 are continuously connected to their corresponding control gates of adjacent NAND cells in the row direction thereby to serve as word lines CG.sub.1 to CG.sub.8 shown in FIGS. 1A and 1B. The first select gates 14.sub.9 and 16.sub.9 are continuously connected in the row direction to serve as a select gate line SG1, as are the second select gates 14.sub.10 and 16.sub.10 to serve as a select gate line SG2. The select gates 14.sub.9, 16.sub.9, 14.sub.10 and 16.sub.10 are constituted by directly connecting the floating and control gates (not shown).
An equivalent circuit of the memory cell array having the above NAND cells arranged in matrix, is illustrated in FIG. 3. Each of source contacts of the NAND cells is connected to its corresponding source line for every group of, e.g., 64 bit lines, and the source line is connected to a reference voltage line formed of aluminum, polysilicon or the like. The reference voltage line is connected to a peripheral circuit. The control gate of the memory cell and the first and second select gates thereof are continuously connected in the row direction.
As shown in FIG. 3, a memory cell group connected to the control gates is usually called one page, while a group of pages between the first and second select lines connected to a pair of select gates on the drain and source is called one NAND block or one block.
For example, one page is constituted of 256-byte or 256.times.8 memory cells, which is called a page size. Data is written to the memory cells of one page at once. One block is constituted of, e.g., 2048-byte or 2048.times.8 memory cells. Data of the memory cells of one block is erased at once.
The constitution and operation of a row decoder for selecting a select gate and a control gate are described in a detail in Japanese Patent Application No. 6-218031.
FIGS. 4A and 4B illustrate a configuration of a prior art NAND type flash memory. As described above, data is written to/read out of the flash memory in units of one page, and data is erased therefrom in units of one block. When a cell array is not divided as shown in FIG. 4A, 256-byte memory cells connected to one word line constitute one page. When a cell array is divided into two cell arrays as shown in FIG. 4B, the memory cells connected to a word line of one of the two cell arrays constitute one page.
For example, the NAND type EEPROM operates as follows. Writing of Data starts from a memory cell farthest from the bit line. A boosted write voltage V.sub.PP (=about 20V) is applied to the control gate of a selected memory cell, and an intermediate voltage (=about 10V) is applied to the control gate and first select gate of a non-selected memory cell. A voltage of OV ("0" writing) or an intermediate voltage ("1" writing) is applied to the bit line in accordance with the data.
The voltage of the bit line is transmitted to the selected memory cell. When data is "0", a high voltage is applied between the floating gate and substrate of the selected memory cell, electrons are tunnel-injected from the substrate to the floating gate, and the threshold voltage moves in the positive direction. When data is "1", no threshold voltage varies.
Data erasure is performed in units of one block. More specifically, all the control and select gates of a block of data to be erased are set to 0V, and a boosted voltage VPPE (about 20V) is applied to a p-well and an n-type substrate. The voltage V.sub.PPE is also applied to the control and select gates of a block of data not to be erased. If the voltage is so applied, electrons are emitted from the floating gate of the memory cell to the well, and the threshold voltage moves in the negative direction.
Data is read out as follows. The bit line is precharged and then goes into a floating state, the control gate of a selected memory cell is set to 0V, the control and select gates of the other memory cells are set to a power supply voltage V.sub.CC (e.g., 3V), and the source line is set to 0V. Whether current flows through the selected memory cell or not is detected by the bit line.
If data written to a memory cell is "0" (threshold voltage V.sub.th of the memory cell &gt;0), the memory cell is turned off and thus the bit line maintains a precharge voltage. If the data is "1" (V.sub.th &lt;0), the memory cell is turned on and the bit line is decreased by .DELTA.V from the precharge voltage. If the bit line voltage is sensed by a sense amplifier, data is read out of the memory cell.
In the semiconductor memory device including the above prior art NAND type EEPROM, the write operation is performed at once for the memory cells connected to the same word line (control gate). The larger the number of memory cells connected to the same word line (or the larger the page size), the higher the write speed per byte.
However, as the page size increases, the erase (block) size increases and the number of blocks included in one chip decreases. As a result, when a large amount of small-sized data, such as data stored in part of one block which is an erase unit, is stored, the amount of data stored in one chip reduces as the page size or the block size increases.
If the page size or the block size varies as the memory size of the EEPROM increases, the compatibility between generations of the memory is lost. For this reason, the design of a system using such a memory has to be changed whenever a generation changes if the page size or block size is varied.